At its recent Advancing AI event, AMD unveiled a comprehensive CPU and accelerator roadmap extending through 2030, reinforcing its long-term strategy for the data center and artificial intelligence markets. Chief Executive Lisa Su highlighted the architectural evolution of the company's Zen microarchitecture, confirming that Zen 7, codenamed Florence, will launch in 2028. Florence will integrate next-generation process technology, advanced memory subsystems, and specialized AI compute extensions. Rather than functioning as a monolithic processor family, Florence will be deployed alongside purpose-built companion platforms, including the Ferrara AI host node and Faenza Agentic Sandbox, enabling tailored solutions for diverse enterprise workloads. Development has already commenced on Zen 8, codenamed Ravenna, which is targeted for a 2030 release. The roadmap follows the recent introduction of the 256-core EPYC 9996 server processor built on the Zen 6 Venice architecture, with its Venice-X variant scheduled for release next year. This structured rollout underscores AMD's commitment to a predictable update cadence, allowing enterprise customers to align infrastructure planning with consistent performance and efficiency gains. On the accelerator front, AMD outlined a significant trajectory for its Instinct series. The upcoming MI500 lineup will feature next-generation High Bandwidth Memory, expanded scale-up domains, and novel copper and optical interconnect technologies. According to Su, this generational leap is projected to deliver more than two thousand times greater inference throughput within a four-year window. Concurrently, the CDNA Next-based MI600 family is in advanced development for a 2028 launch. The event also saw the commercial release of the MI455X GPU and preliminary details regarding the MI500X series, slated for introduction in the coming year. Collectively, these announcements position AMD to directly challenge incumbent leadership in high-performance computing and AI training workloads while diversifying its server CPU portfolio to meet evolving architectural demands.