IBM Unveils First Dual-ISA Core for 2nm Mainframe at Hot Chips 2026

At Hot Chips 2026, IBM unveiled its next-generation mainframe processor, marking a significant architectural shift with the industry’s first dual-ISA core capable of natively executing both z/Architecture and AArch64 instructions within a single silicon unit. Developed for the upcoming z18 mainframe line, the chip represents a departure from traditional heterogeneous designs, allowing dynamic instruction set switching in nanoseconds rather than isolating workloads across separate cores. Built on a 2-nanometer process, the new processor features 11 cores operating at a 5.7 GHz base frequency, surpassing the specifications of the current Telum II architecture. The core design integrates a 36 MB private L2 cache, alongside expanded virtual L3 and L4 caches. To enable seamless ARM execution, IBM leverages Linux Kernel-based Virtual Machine technology, which handles AArch64 instructions while standard z/Architecture instructions bypass the virtualization layer entirely. This approach preserves mainframe-grade reliability, with IBM projecting 99.999999 percent uptime, equating to approximately 0.032 seconds of annual downtime. Microarchitecturally, the design repurposes existing branch prediction and translation lookaside buffers while introducing substantial silicon expansion for AArch64 decoding and support for ARM v9.3 Scalable Vector Extensions. General-purpose register renaming and arithmetic units were adapted to share data flow pathways, with new hardware structures implemented for floating-point and vector workloads. Alongside the central processor, IBM presented its next-generation Spyre AI accelerator. The updated unit incorporates 16 cores optimized for emerging AI data formats, including FP4 and MXFP4. The most significant enhancement lies in its memory subsystem, which transitions from LPDDR5 to 96 gigabytes of HBM3e. This upgrade delivers up to 4 terabytes per second of bandwidth, representing a twentyfold increase over previous implementations and positioning the accelerator for high-throughput machine learning workloads. The processor also retains an on-chip data processing unit and dedicated hardware accelerators for compression and cryptography. The dual-ISA architecture directly addresses a persistent industry challenge: the mainframe ecosystem’s historical alignment with legacy workloads, which has increasingly lagged behind modern AI and software development pipelines that prioritize ARM targets. Tina Tarquinio, chief product officer for IBM Z and LinuxONE, emphasized that native ARM execution eliminates the need for costly software porting, allowing ARM-based virtual machines to operate with true silicon parity. This capability aims to integrate mainframes into contemporary AI architectures without compromising their mission-critical reliability. IBM typically cycles mainframe releases every two and a half to three years. While the new silicon is slated for the z18 platform, commercial deployment will follow a phased, customer-driven timeline typical of enterprise infrastructure procurement.