Nvidia Unveils Next-Gen CPO as Optical Competition Shifts to Chip Packaging

Nvidia used SEMICON West 2026 in San Francisco to detail its next-generation co-packaged optics roadmap, introducing Optics-on-Interposer, a research-stage architecture that moves the optical engine from the package substrate onto the same silicon interposer used by the compute chip. Researcher Nikola Nedovic said the approach shortens high-speed electrical paths, reduces power consumption, and increases interconnect density by letting optical engines and ASICs or GPUs connect through denser interposer routing while bypassing organic substrate in critical signal paths. The company also disclosed dense wavelength division multiplexing work using eight wavelengths in a single fiber to reach 256Gb/s aggregate bandwidth. The push builds on CPO products already moving into volume. In June Nvidia began mass production of Spectrum-X Ethernet Photonics switches for the Vera Rubin platform, including SN6800 with 512 800Gb/s ports and 409.6Tb/s switching capacity. Nvidia claims CPO cuts relevant power per 1.6Tb/s port by about 80% versus pluggable modules. Yet AI clusters and faster SerDes lanes are making even package-level electrical routing costly. OOI aims to solve that next bottleneck by using the interposer the way GPUs use it for HBM: a high-density bridge between silicon chips and co-packaged optical engines. Commercialization remains open-ended. Nvidia has not given an OOI timeline, cost, power or density target. Existing CPO supply chains are expanding: on October 21 Nvidia and OSAT partner Siliconware Precision Industries said they plan to raise CPO optical engine capacity 15-fold by mid-2027 and double it again by end-2028. That scale-up underscores why manufacturing is becoming central to optical networking. Putting optical engines nearer thermal-sensitive silicon increases demands on thermal control, assembly yield, fiber alignment, and repair economics. Nvidia’s first CPO switches already use reflow-tolerant optical engines, detachable fiber connectors and external laser sources to ease test and service; OOI would raise the bar further. Test complexity is another constraint. TrendForce says optical alignment steps can take seconds, while full photonics chip testing can exceed 100 seconds because each device must be evaluated across wavelengths, power, loss and temperature. CPO production therefore requires tighter integration of automated test equipment, light sources, power meters, spectrometers and precision alignment tools, with 2027 expected as a key year for test-platform consolidation. The shift also reshapes industry structure. Legacy pluggable-module makers are not obsolete, but advanced packaging, silicon photonics and optoelectronic co-design are becoming core competencies. TSMC provides silicon photonics and COUPE packaging technology, SPIL handles assembly and test, Lumentum and Coherent supply external lasers, and Foxconn participates in system integration. In China, companies such as TFC Optical Communications are shipping fiber array units and external laser sources for CPO, while Innolight and Eoptolink are expanding silicon photonics and next-generation module work. Equipment makers, including ficonTEC, are winning orders for wafer and die-level CPO test systems. Nvidia’s message is that optical interconnect competition is no longer only about modules or wavelengths. As CPO enters volume and OOI moves closer to adoption, advantage will depend on co-packaging, thermal management, yield, test throughput, and supply-chain coordination across foundry, OSAT, optical component, and system vendors.