This dataset is the ChiPBench dataset for chip physical layout jointly released by researchers from USTC MIRA Lab and Huawei Noah's Ark Lab in 2024. The relevant paper is "Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms".

ChiPBench is a comprehensive benchmark specifically designed to evaluate the effectiveness of existing AI-based chip layout algorithms in improving the final design PPA metric. Specifically, the research team collected 20 circuits from different fields such as CPU, GPU, and microcontroller. These designs are compiled by executing workflows from Verilog source code, retaining the necessary physical implementation kit, which can evaluate the impact of layout algorithms on the final design PPA.