SiPearl Taps €32 Million to Finalize Rhea1 HPC CPU Tapeout, Eyes Mixed Memory Architecture for 2026 Launch

SiPearl, a French chip design company, has made significant strides in developing high-performance computing (HPC) and AI-centric CPUs with the announcement of the Rhea1 tapeout and the successful closure of a €32 million third tranche of its Series A funding round, bringing the total funding to €130 million ($152.3 million). Launched in January 2020 under the European Processor Initiative (EPI), the Rhea1 project aims to create an indigenous European solution to reduce dependency on NVIDIA GPUs and other foreign technologies in HPC and AI applications. With 200 chip designers spread across France, Spain, and Italy, SiPearl has developed the Rhea1 CPU, featuring 80 Neoverse V1 Zeus cores and 61 billion transistors. The chip is fabricated using TSMC's N6 6-nanometer process, and customer sampling is expected by early 2026. The Rhea1 is designed to be a versatile CPU capable of handling both standalone HPC tasks and serving as an adjunct to GPUs from NVIDIA and AMD. It will be initially deployed in the Universal Cluster segment of the Jupiter supercomputer at Forschungszentrum Jülich in Germany. This cluster will consist of over 1,300 two-socket Rhea1 nodes, while the bulk of the Jupiter's compute power will come from the GPU Booster module, featuring 23,536 NVIDIA Hopper H200 GPUs paired with Grace CG100 Arm CPUs. One of the Rhea1's standout features is its mixed memory architecture, combining DDR5 and HBM to enhance memory bandwidth and compute efficiency. This approach is similar to the A64FX processor used in Japan's Fugaku supercomputer and India's Aum chip, both of which also employ a dual memory system. The importance of mixed memory architectures in HPC is evident from the performance gains seen in Intel's Xeon Max processor, where switching from DDR5 to HBM2E memory doubled the chip's work output on certain benchmarks. SiPearl's ability to integrate both DDR5 and HBM into the Rhea1 is particularly notable, as it addresses a critical need for HPC applications that are often memory-bound. While Intel and AMD have focused on different aspects of HPC and AI, SiPearl's innovative approach offers a promising alternative for organizations seeking a 1.8X speedup on memory-bandwidth-limited applications. Looking ahead, SiPearl is planning to develop the Rhea2 chip and subsequent "Kronos" improvements. To fund these endeavors, the company is targeting a Series B funding round of €200 million ($234.4 million) between 2026 and 2028. The third tranche of Series A funding included contributions from Cathay Venture, the European Innovation Council Fund, and the French government, in addition to existing investors like Arm Holdings and Atos. Industry insiders view SiPearl's progress with optimism, seeing the company's mixed memory architecture as a potential game-changer in the HPC market. By addressing memory bandwidth limitations, SiPearl could offer a viable alternative to existing solutions, particularly for applications where memory throughput is a bottleneck. As HPC continues to evolve, the integration of high-bandwidth memory in CPU designs is becoming increasingly essential, and SiPearl's approach is seen as a strong contender in this space. SiPearl's commitment to remaining independent and its strategic focus on European autonomy in CPU design reflect a broader trend of regional technology initiatives aimed at reducing reliance on foreign components. If the Rhea1 and future chips perform well, they could play a crucial role in Europe's efforts to bolster its presence in the global HPC and AI industries.