Huawei Patents Quad-Chiplet AI Accelerator Design, Rumored to Rival Nvidia’s H100 and TSMC’s Advanced Packaging Tech

Huawei has filed a patent for a quad-chiplet design that appears to be aimed at its next-generation AI accelerator, the Ascend 910D. The patent's details closely mirror the design approach of Nvidia’s quad-chiplet Rubin Ultra, but it also hints at advanced chip packaging techniques that could rival those developed by TSMC, the current market leader in semiconductor manufacturing. The core focus of Huawei's patent revolves around the interconnection technology used to link the compute chiplets. Instead of relying on traditional interposers, the design suggests the use of bridge-like structures, similar to TSMC’s CoWoS-L or Intel’s EMIB with Foveros 3D. These techniques allow for more efficient and compact integration of multiple chips, which is crucial for high-performance AI workloads. The Ascend 910D is also expected to be equipped with HBM-class memory modules, further enhancing its capabilities. Speculation surrounding the Ascend 910D began in April, and recent patent filings are adding weight to these rumors. The single-die version of the Ascend 910B is known to have a die size of 665 mm². If the 910D indeed uses a quad-chiplet design, its total die size could reach approximately 2,660 mm². Each 910B chiplet includes four HBM memory modules, totaling 85 mm² each. Therefore, the 910D would likely have 16 HBM modules, increasing the memory footprint to around 1,366 mm². Combining these elements, the total silicon area required for the 910D could be around 4,020 mm², which is equivalent to five EUV reticle sizes according to TSMC standards. TSMC is scheduled to introduce such large packaging solutions for volume production in 2026. This development is significant because, although SMIC and Huawei lag behind TSMC in lithography technology, they may be on par when it comes to advanced packaging. By leveraging these packaging techniques, Chinese companies could potentially bypass US export restrictions that limit their access to the latest chip manufacturing technologies. Advanced packaging allows multiple older-process-node chiplets to be combined, achieving performance levels comparable to single-chip designs produced with leading-edge nodes. The patent filings also hint at future plans beyond the 910D. Huawei is reportedly working on another processor, tentatively named Ascend 920, which is expected to compete with Nvidia’s upcoming H20 GPU. However, the naming convention here is somewhat inconsistent, suggesting that such reports should be taken with a grain of salt. Industry insiders are beginning to acknowledge the potential of Huawei's quad-chiplet design and advanced packaging techniques. If successful, the Ascend 910D could significantly boost Huawei's position in the AI accelerator market, potentially outperforming Nvidia’s H100 in GPU package performance. This would mark a significant step forward for Huawei and possibly set a new standard for advanced chip packaging and multi-chip designs in the industry. Huawei’s advancements in chip packaging and multi-chiplet designs are particularly noteworthy given the ongoing geopolitical tensions and trade restrictions. The company has faced numerous Challenges due to US sanctions, which have limited its access to cutting-edge semiconductor technology. By focusing on advanced packaging, Huawei is demonstrating a strategic shift towards self-reliance and innovation, potentially paving the way for other Chinese tech firms to follow suit. While not all patent applications result in commercial products, the detailed nature of Huawei's filings and the alignment with industry trends suggest a strong possibility that the Ascend 910D could become a reality. If it does, it could represent a significant milestone in Huawei’s efforts to maintain technological leadership in AI hardware, despite external constraints.