Intel Unveils Complex Chiplet Design in Arrow Lake Die Shots, Revealing TSMC Fabrication and Core Configuration Innovations

Recent die shots of Intel’s Arrow Lake architecture, shared by Andreas Schiling on X, offer a detailed look at the company’s chiplet-based design. The images reveal the intricate layout of the individual tiles and the core configurations within the compute tile of Intel’s upcoming desktop Core Ultra 200S series CPUs. The full die of the Core Ultra 200S series is prominently displayed, with the compute tile situated at the upper left, the IO tile at the bottom, and the SoC and GPU tiles on the right. Two filler dies, located at the bottom left and top right, are included to provide structural rigidity to the overall chip. The compute die, manufactured on TSMC’s cutting-edge N3B node, spans an area of 117.241 square millimeters. In contrast, the IO and SoC tiles are produced on TSMC’s more mature N6 node, with the IO tile measuring 24.475 square millimeters and the SoC tile 86.648 square millimeters. These tiles sit on an underlying base tile fabricated using Intel’s 22nm FinFET process. Notably, Arrow Lake marks the first time Intel has relied almost entirely on a competitor’s fabrication nodes for its architecture, except for the base tile. The IO tile houses critical components such as the Thunderbolt 4 controller, display PHY, PCIe Express buffers, and PHYs. Meanwhile, the SoC tile includes the display engines, media engine, additional PCIe PHYs, buffers, and DDR5 memory controllers. The GPU tile, another significant element, features four Xe GPU cores and an Xe LPG (Arc Alchemist) render slice, enhancing the chip’s graphics capabilities. One of the standout features of Arrow Lake’s core configuration is the integration of E-cores between the P-cores, a departure from previous hybrid architectures where E-cores were clustered separately. This arrangement aims to mitigate thermal hotspots. Specifically, four out of the eight P-cores are positioned along the borders of the die, with the remaining four in the center. The E-cores are divided into four clusters, each housing four cores and sandwiched between the outer and inner P-cores. Schiling’s die shots also provide insights into the cache layout of Arrow Lake. Each P-core is equipped with 3MB of L3 cache, totaling 36MB across all P-cores. The E-cores, organized into clusters, share 3MB of L2 cache per cluster, with 1.5MB dedicated to pairs of cores. An interconnect facilitates the linking of the two L2 cache clusters and connects each core cluster to the ring agent. A notable improvement is the shared L3 cache connectivity between the E-cores and P-cores, which was absent in previous designs. Despite its innovative design, Intel’s initial implementation of Arrow Lake has faced criticism over latency issues caused by the interconnect responsible for linking the various tiles. The company is addressing these concerns through firmware updates, but currently, the performance of Arrow Lake cannot match that of AMD’s Ryzen 9000 series, particularly the 9800X3D, or even Intel’s own 14th-generation processors like the 14900K in gaming scenarios. However, the shift to a chiplet-based approach represents a significant step forward for Intel. This modular design allows each tile to be developed and optimized independently, using different fabrication nodes. The benefits include improved yield rates, better development flexibility, and reduced production costs. By adopting this strategy, Intel can fine-tune its future architectures more efficiently, potentially leading to advancements that address current limitations and enhance overall performance. In summary, while Intel’s Arrow Lake architecture is highly complex and offers new possibilities for optimization, it currently faces performance challenges that the company is working to resolve. The chiplet design, however, is a promising direction that could pave the way for more competitive and cost-effective processors in the future.