Cadence Enhances IP Portfolio for Intel 18A and 18A-P, Boosting AI, HPC, and Mobility Designs

Cadence, a leading provider of electronic design automation (EDA) solutions, has significantly expanded its design IP portfolio to be optimized for Intel 18A and Intel 18A-P technologies. This move, announced during the Intel Foundry Direct Connect event, underscores Cadence’s strategic partnership with Intel Foundry and its commitment to advancing AI, high-performance computing (HPC), and advanced mobility applications. Key Developments Expanded Design IP Portfolio Cadence’s new IP offerings for Intel 18A and 18A-P technologies include: 112G Extended Long-Reach SerDes: Superior bit error rate (BER) performance for data integrity over extended distances. 64G MP PHY: Supports PCIe 6.0, CXL 3.0, and 56G Ethernet, enhancing data transfer speeds and reliability. LPDDR5X/5 Memory Controller and PHY: Operates at 8533 Mbps with multi-standard support, providing efficient memory management. UCIe 1.0 16G: Facilitates advanced packaging and interconnectivity, crucial for modern multi-chiplet designs. These IP solutions are designed to maximize power, performance, and area (PPA) efficiency, enabling faster time-to-market for sophisticated SoC designs. The IP is specifically tailored to leverage Intel’s RibbonFET gate-all-around transistors and PowerVia backside power delivery network, which are key features of the 18A nodes. Certification of Design Solutions Cadence’s comprehensive AI-driven digital and analog/custom design solutions have also been certified for the latest Intel 18A process design kit (PDK). This certification covers a wide range of tools, including: Cerebrus® Intelligent Chip Explorer Genus™ Synthesis Solution Innovus™ Implementation System Quantus™ Extraction Solution Quantus Field Solver Tempus™ Timing Solution Pegasus™ Verification System Virtuoso® Studio Spectre® Platform Voltus™-XFi Custom Power Integrity Solution This suite of tools forms a complete RTL-to-GDS flow, ensuring that designers can work seamlessly from the initial design phase to final production, all while meeting stringent performance and efficiency benchmarks. Early Collaboration for Future Nodes Beyond the immediate enhancements for the Intel 18A/18A-P nodes, Cadence and Intel Foundry are already engaged in early design technology co-optimization for the upcoming Intel 14A-E node. This proactive collaboration aims to ensure that Cadence’s EDA flows are ready for the next generation of advanced processes, thereby maintaining the momentum of innovation and customer support. Advanced Packaging Workflow Cadence and Intel Foundry have jointly developed an advanced packaging workflow using Intel’s Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology. This workflow simplifies the integration of complex multi-chiplet designs by eliminating data conversion, shortening design cycles, and enabling early thermal, signal integrity, and power modeling. The focus is on streamlining the integration process and reducing risks associated with adopting new technologies. Strategic Partnerships and Programs Cadence continues to support the Intel Foundry Accelerator Alliance Program and has recently joined the Intel Foundry Chiplet Alliance Program as a founding member. This new alliance will help ensure that Cadence’s solutions facilitate the deployment of interoperable and secure chiplet solutions for various applications and markets. Cadence is already a participant in the EDA, IP, Design Services, and USMAG Alliances, further solidifying its role within the Intel ecosystem. Industry Insights Industry experts are optimistic about the implications of this expanded partnership. The collaboration between Cadence and Intel Foundry is seen as a critical step in addressing the growing demand for high-performance, low-power SoCs in AI, HPC, and mobility sectors. By integrating the latest innovations in IP and EDA tools, Cadence is positioning itself to become a cornerstone in the development of next-generation silicon solutions. Intel Foundry’s Suk Lee highlighted the synergy between the two companies, stating, "The combination of Cadence's innovative IP solutions and Intel 18A and 18A-P technologies delivers significant advantages for AI/ML and HPC applications. This partnership accelerates the development of high-performance solutions and empowers our mutual customers to achieve unparalleled PPA efficiencies and speed up their time to market." Company Profile Cadence Design Systems, Inc., headquartered in San Jose, California, is a global leader in EDA and software solutions for semiconductor and electronics companies. Recognized for its pioneering work in AI and digital twins, Cadence’s Intelligent System Design™ strategy integrates computational software across various stages of the design process. In 2024, Cadence was named one of the world's top 100 best-managed companies by the Wall Street Journal, reflecting its dedication to excellence and innovation. For more information on Cadence and its partnership with Intel Foundry, visit the Intel Foundry partner webpage.