AMD's Next-Gen EPYC 9006 Venice CPUs Could Pack Up to 256 Zen 6c Cores, Leaks Suggest

Recent reports suggest that AMD’s sixth-generation EPYC 9006 “Venice” CPUs could come equipped with an astounding 256 cores, based on the Zen 6c architecture, and 1GB of L3 cache—without any extra 3D cache. However, these details should be taken with a grain of salt, as the products are still likely one to two years away from release. AMD’s current-generation Zen 5-based server EPYC 9005 CPUs, codenamed Turin, fit into the SP5 socket, much like the EPYC 9004 (Genoa) series, which uses Zen 4 cores. These Turin CPUs are available with denser Zen 4c/5c cores, capable of reaching up to 192 cores and 384 threads. Additionally, AMD offers a more cost-effective SP6 socket, compatible with the EPYC 8004 (Siena) series that supports up to 64 Zen 4c cores. There are also rumors that this socket will support the upcoming Zen 5-based EPYC 8005 (Sorano) family. For the next generation, AMD is rumored to introduce new SP7 and SP8 sockets, building upon the current SP5 and SP6 platforms. The SP7 socket is expected to house the EPYC 9006 (Venice) CPUs, which are said to feature up to 256 Zen 6c cores. These cores are spread across eight chiplets, each containing 32 cores and 128MB of L3 cache, resulting in 1GB of total L3 cache for the 256-core configuration. The specifications for standard Zen 6-based Venice CPUs on the SP7 socket remain unclear, but the leak indicates a substantial enhancement in the chiplet design. Each Zen 6 chiplet is rumored to have 12 cores and 48MB of L3 cache, marking a significant step up from the eight cores and 32MB of L3 cache found in Zen 2 and subsequent generations. On the lower-cost SP8 socket, four 32-core Zen 6c chiplets are projected to provide 128 cores and 512MB of total L3 cache. This represents a notable improvement over the current Siena and Sorano offerings. Standard Zen 6 configurations on the SP8 socket are expected to offer 96 cores (across eight 12-core chiplets) and 384MB of L3 cache. These advancements in core density and cache size are likely driven by the adoption of TSMC’s 2nm (N2) process node, which promises high performance and efficiency gains. Along with the core and cache enhancements, AMD is also expected to improve other aspects of the CPUs, such as increasing the number of memory channels and PCIe lanes. AMD’s push for more cores and larger caches is partly a strategic response to Intel’s upcoming Diamond Rapids and Clearwater Forest Xeon processors, which are expected to be highly advanced designs. To stay competitive, AMD may also adopt advanced packaging technologies from TSMC, such as silicon interposers (CoWoS-S) or silicon bridges (InFO_LSI or CoWoS-L), to connect the chiplets and input/output die (IOD). Following AMD’s usual two-year development cycle between CPU generations, the first Zen 6-based products are projected to launch by the second half of 2026. Stay tuned to Tom's Hardware for the latest updates and insights on these exciting developments. Make sure to follow us on Google News to keep track of all our news, analysis, and reviews.